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ADuC7060
FIQSTA Register
?
Vectored interrupts—allows a user to define separate
Name:
Address:
FIQSTA
0xFFFF0100
interrupt service routine addresses for every interrupt
source. This is achieved by using the IRQBASE and
IRQVEC registers.
Default value:
Access:
0x00000000
Read only
?
IRQ/FIQ interrupts—can be nested up to eight levels
depending on the priority settings. An FIQ still has a
higher priority than an IRQ. There fore, if the VIC is
PROGRAMMED INTERRUPTS
Because the programmed interrupts are not maskable, they are
enabled for both the FIQ and IRQ and prioritization is
maximized, then it is possible to have 16 separate interrupt
levels.
controlled by another register (SWICFG) that writes into both
?
Programmable interrupt priorities—using the IRQP0 to
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
SWICFG
The 32-bit register dedicated to software interrupt is SWICFG,
described in Table 64. This MMR allows the control of a
programmed source interrupt.
SWICFG Register
IRQP2 registers, an interrupt source can be assigned an
interrupt priority level value between 1 and 8.
VIC MMRS
IRQBASE
The vector base register, IRQBASE, is used to point to the start
address of memory used to store 32 pointer addresses. These
pointer addresses are the addresses of the individual interrupt
Name:
Address:
SWICFG
0xFFFF0010
service routines.
IRQBASE Register
Default value:
Access:
0x00000000
Write only
Name:
Address:
Default value:
IRQBASE
0xFFFF0014
0x00000000
Table 64. SWICFG MMR Bit Designations
Bit Description
Access:
Read and write
31 to 3
2
Reserved.
Programmed interrupt FIQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of FIQSTA and
Table 65. IRQBASE MMR Bit Designations
Bit Type Initial Value Description
FIQSIG.
31:16
Read only
Reserved
Always read as 0
1
Programmed interrupt IRQ. Setting/clearing this bit
15:0
R/W
0
Vector base address
corresponds to setting/clearing Bit 1 of IRQSTA and
IRQSIG.
IRQVEC
0
Reserved.
The IRQ interrupt vector register, IRQVEC points to a memory
Any interrupt signal must be active for at least the minimum
interrupt latency time to be detected by the interrupt controller
and to be detected by the user in the IRQSTA/FIQSTA register.
VECTORED INTERRUPT CONTROLLER (VIC)
The ADuC7060 incorporates an enhanced interrupt control
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should only be read when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
IRQVEC Register
system or vectored interrupt controller. The vectored interrupt
controller for IRQ interrupt sources is enabled by setting Bit 0
of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables
the vectored interrupt controller for the FIQ interrupt sources.
The vectored interrupt controller provides the following
enhancements to the standard IRQ/FIQ interrupts:
Name:
Address:
Default value:
Access:
IRQVEC
0xFFFF001C
0x00000000
Read only
Rev. 0 | Page 56 of 100
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